TIMMER IC 555 AND ITS INTERNAL BLOCK DIAGRAM

 

Description:-

The timer IC 555 circuit consists of two comparator A1 and A2, an S-R flip-flop, and a transistor Q1 that operates as a switch. One power supply is required for operation with the supply voltage typically 5V. A resistive voltage divider, consisting of the three equal valued 5k resistors. is connected across Vcc and establishes the reference (threshold) voltages for the two comparators. These are Vth=2/3Vcc for comparator A1 and Vtl=1/3Vcc for comparator A2.

In this circuit, S-R flip-flop is a bistable circuit having complementary outputs, denoted Q and Q'. Inset state, the o/p at Q is "high" (approximately equal to Vcc) and that at Q' is "low"(approximately equal to 0v). In other Stable State, termed the reset state, the o/p at Q is "low" and that at Q' is "high". The flip-flop is set by applying a high level(Vcc) to its set input terminal, labelled as S. to reset the flip-flop, a high level is applied to the reset input terminal, labelled R.

The reset and set input terminal of a flip-flop in 555 timer IC circuit are connected to the outputs of comparator A1 and comparator A2 respectively.
The +ve i/p terminal of comparator A1 is brought out to an external terminal of the 555 packages, labelled threshold. Similarly, the -ve i/p terminal of comparator A2 is connected to an external terminal labelled trigger and the collector of transistor Q is connected to a terminal labelled discharge. finally, the Q o/p of a flip-flop is connected to the o/p terminal of the timer package labelled out.